* LDEBR test $Id$
sysclear
archmode esame
r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
r 1d0=0000000180000000000000000000025A # z/Arch pgm new PSW
r 200=B7000320     # LCTL R0,R0,CTLR0  Set CR0 bit 45
r 204=B29D0324     # LFPC FPCREG       Load value into FPC register
r 208=D7FF09000900 # XC RES1,RES1      Clear result table
r 20E=41000006     # LA R0,6           R0=Number of test data
r 212=41100800     # LA R1,TEST1       R1=>Test data table
r 216=41F00900     # LA R15,RES1       R15=>Result table
r 21A=1B88         # SR R8,R8          Clear CC register
r 21C=78201000     #A LE R2,0(,R1)     Load R2=TESTn
r 220=B29D1004     # LFPC 4(R1)        Load FPC=TESTn+4
r 224=B3040032     # LDEBR R3,R2       Lengthen R2 giving R3
r 228=B2220080     # IPM R8            R8=Cond code and pgm mask
r 22C=6030F000     # STD R3,0(,R15)    Store R3 in result table
r 230=5080F008     # ST R8,8(,R15)     Store CC in table
r 234=41F0F010     #B LA R15,16(,R15)  R15=>next result table
r 238=41101008     # LA R1,8(,R1)      R1=>Next TESTn
r 23C=4600021C     # BCT R0,A          Loop to end of TEST table
r 240=41000900     # LA R0,RES1        R0->Actual results
r 244=41100060     # LA R1,6*16        R1=Length of results table
r 248=41200C00     # LA R2,EXP1        R2->Expected results
r 24C=41300060     # LA R3,6*16        R3=Length of results table
r 250=0F02         # CLCL R0,R2        Compare with expected results
r 252=477002FC     # BNE DIE           Error if not equal
r 256=B2B20300     # LPSWE WAITPSW     Load enabled wait PSW
r 25A=B29C0324     #PGM STFPC FPCREG   Save FPC register
r 25E=6030F000     # STD R3,0(,R15)    Store R3 in result table
r 262=D203F008032C # MVC 8(4,R15),EYE  Move eye-catcher to result table
r 268=D200F00D0326 # MVC 13(1,R15),FPCREG+2  Save DXC in result table
r 26E=D201F00E008E # MVC 14(2,R15),PGMINT+2  Save interrupt code in result table
r 274=47F00234     # B B               Continue to next test
r 2FC=B2B20310     #DIE LPSWE DISWAIT  Load disabled wait PSW
r 300=07020001800000000000000000AAAAAA # WAITPSW Enabled wait state PSW
r 310=00020001800000000000000000BADBAD # DISWAIT Disabled wait state PSW
r 320=00040000     # CTLR0             Control register 0 (bit45 AFP control)
r 324=00000000     # FPCREG            Floating point control register
r 328=00000000     # COUNT             Error counter
r 32C=FEEDBEEF     # EYE               Eye-catcher
* Test data
r 800=42F6000080000000                 # TEST1 DC EB'123' FPC MASK=80
r 808=C2F6000080000000                 # TEST2 DC EB'-123' FPC MASK=80
r 810=7F80000080000000                 # TEST3 DC EB'INF' FPC MASK=80
r 818=7F80000280000000                 # TEST4 DC EB'SNAN(00002)' FPC MASK=80
r 820=7F80000200000000                 # TEST4 DC EB'SNAN(00002)' FPC MASK=00
r 828=7FC0000080000000                 # TEST5 DC EB'QNAN(0)' FPC MASK=80
* Expected results, condition codes, and DXC codes
r C00=405EC000000000000000000000000000 # EXP1 DC DB'123'
r C10=C05EC000000000000000000000000000 # EXP2 DC DB'-123'
r C20=7FF00000000000000000000000000000 # EXP3 DC DB'INF'
r C30=7FF0000040000000FEEDBEEF00800007 # EXP4 DC DB'SNAN(00002)',EYE,DXC=80,PGMINT=0007
r C40=7FF80000400000000000000000000000 # EXP4 DC DB'QNAN(00002)'
r C50=7FF80000000000000000000000000000 # EXP5 DC DB'QNAN(0)'
pgmtrace +7
restart
pause 1
* Display test data
r 800.30
* Display expected results
r C00.60
* Display actual results
r 900.60
