* AXTR test $Id$
sysclear
archmode esame
r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
r 1d0=0002000180000000000000000000DEAD # z/Arch pgm new PSW
r 200=B700023C     # LCTL R0,R0,CTLR0  Set CR0 bit 45
r 204=EB2502400004 # LMG R2,R5,PACKED  Load R2,R3=PACKED1 R4,R5=PACKED2
r 20A=B3FB0042     # CXSTR R4,R2       Load FPR R4,R6 from PACKED1 R2,R3
r 20E=B3FB0014     # CXSTR R1,R4       Load FPR R1,R3 from PACKED2 R4,R5
r 212=B3DA1094     # AXTR R9,R4,R1     Add FPR R4,R6 + R1,R3 giving R9,R11
r 216=B3EB00A9     # CSXTR R10,R9,0    Convert FPR R9,R11 to PACKED R10,R11
r 21A=B3EB01C9     # CSXTR R12,R9,1    Convert FPR R9,R11 to PACKED R12,R13 
r 21E=EBAD02600024 # STMG R10,R13,RESULTC  R10,R11=>RESULTC R12,R13=>RESULTF
r 224=D51F026002B0 # CLC RESULTC(32),EXPECTC  Compare with expected results
r 22A=A7740004     # JNE *+8           Error if not equal
r 22E=B2B20300     # LPSWE WAITPSW     Load enabled wait PSW
r 232=B2B20310     # LPSWE DISWAIT     Load disabled wait PSW
r 23C=00040000     # CTLR0             Control register 0 (bit45 AFP control)
r 240=0000000000000000000000000000001C # PACKED1  DC PL16'1'
r 250=0000000000000000000000000000002C # PACKED2  DC PL16'2'
r 260=FEEDFEEDFEEDFEEDFEEDFEEDFEEDFEED # RESULTC should be PL16'3' (with sign C)
r 270=FEEDFEEDFEEDFEEDFEEDFEEDFEEDFEED # RESULTF should be PL16'3' (with sign F)
r 2B0=0000000000000000000000000000003C # EXPECTC PL16'3' (with sign C)
r 2C0=0000000000000000000000000000003F # EXPECTF PL16'3' (with sign F)
r 300=07020001800000000000000000AAAAAA # WAITPSW Enabled wait state PSW
r 310=00020001800000000000000000BADBAD # DISWAIT Disabled wait state PSW
ostailor null
restart
pause 1
* Display expected results
r 2B0.20
* Display actual results
r 260.20
